View CS48520-CQZR_4916378.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? copyright 2006 cirrus logic, inc. dec ?06 confidential ds734a3 http://www.cirrus.com cs48500 data sheet advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. confidenti al draft de lp h i features ? cost-effective, high-performance 32-bit dsp ? 300,000,000 mac/s (multiply accumulates per second) ? dual mac cycles per clock ? 72-bit accumulators are the most accurate in the industry ? 24k x 32 sram, 2k blocks - assignable to data or program ? internal rom contains a va riety of configurable sound enhancement feature sets ? 8-channel internal dma ? internal watch-dog dsp lock-up prevention ? dsp tool set w/ private keys for protecting customer ip ? configurable serial audio inputs/outputs ? configurable for all input/output types ? maximum 32-bit @ 192 khz ? supports 32-bit audio sample i/o between dsp chips ? tdm input modes (multiple channels on same line) ? 192 khz spdif transmitter ? multi-channel dsd direct stream digital sacd input ? supports two different input fs sample rates ? output can be master or slave ? dual processing path capability ? input supports dual domain slave clocking ? hardware assist time sampling for sample rate conversion ? integrated clock manager/pll ? can operate from external crystal, external oscillator ? input fs auto detection ? host & boot via serial interface ? configurable gpios and external interrupt input ? 1.8v core / 3.3v i/o that are +5v tolerant ? low-power mode ? "energy-star ready" via low-power mode, 350uw in standby 32-bit dsp d m a p x y serial control 1 12 ch pcm audio out gpio debug watchdog tmr1 tmr2 pll s/pdif 12 ch. audio in / 6 ch. sacd in differentiating from the legacy cirrus multi-standard, multi- channel decoders, this new cs48500 family is still based on the same high-performance 32-bit fixed point dsp digital signal processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associated with multi-channel and virtual-channel sound enhancements. target applications are: ? digital televisions ? multimedia peripherals ?ipod ? docking stations ? automotive head units ? automotive outboard amplifiers ? hd-dvd & blu-ray disc dvd receivers ? pc speakers in these applications there are a wide variety of licensable dsp ip codes available today from: cirrus also has developed, or is developing their own royalty- free versions of popular features sets like cirrus bass manager, cirrus dynamic volume leveler, cirrus original multichannel surround, cirrus virtual speaker & cirrus 3d- audio. the cs48500 is programmed using the cirrus proprietary dsp composer? gui development tool. processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio dsp prim itives. the end result is a software image that is down-loaded to the dsp via serial host or serial boot modes. ordering information: see page 23 for ordering information ? w tm
cs48500 data sheet 32-bit audio decoder dsp family 2 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com . important notice "advance" product information describes products that are in deve lopment and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") be- lieve that the information contained in this document is accurate and reliable. however, the information is subject to change w ithout notice and is provided "as is" without warranty of any kind (express or implied). customers are ad vised to obtain the latest vers ion of relevant information t o verify, before placing orders, that infor- mation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at t he time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this infor- mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trad emarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend t o other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor pr oducts may involve potential risks of death, pe rsonal injury, or severe proper- ty or environmental damage ("critical ap plications"). cirrus produc ts are not designed, authorized or warranted for use in aircraft systems, military applications, products surg ically implanted in to the body, automotive sa fety or security devices, life support products or other critical applications. inclus ion of cirrus products in such appl ications is understood to be fully at the customer's risk and cirrus di sclaims and makes no warranty , express, stat utory or implied, in cluding the implied warranties of merchantability and fitness fo r particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's cus tomer uses or permits the use of cirrus products in critical applications, cus- tomer agrees, by such use, to fully indemnify cirrus, its office rs, directors, emplo yees, distributors and other agents from any and all liability, including attorneys' fees and costs, th at may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, dsp composer, and cirrus framework are trademarks of cirrus logic, inc. a ll other brand and product names in this document may be trademarks or service marks of their respective owners. dolby, dolby digital, dolby headphone, dolby virtual speaker, dolby headphone, and pro logic are registered trademarks of dolby laboratories, inc. supply of an implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or int ellectual property right of dolby lab- oratories, to use the implementation in any finished end-user or ready-to-use final product. it is hereby notified that a lice nse for such use is required from dolby laboratories. dts is a registered trademark of the digital theater systems, inc. dts neo:6 is a trademark of digital theater systems, inc. it is hereby notified that a third-party license from dts is necessary to distribute software of dt s in any finished end-user or ready-to-use final product. srs, circle surround and trusurround xt are registered trademarks of srs labs, inc. circle surround ii is a trademark of srs l abs, inc. the circle surround technology rights incorporated in the cirrus logic chip are owned by srs labs, inc. and by valence technology ltd., and license d to cirrus logic, inc. users of any cirrus logic chip containing enabled circle surround technolo gy? (i.e., circle surround? licensees) must first sig n a license to pur- chase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sampl e to, and the satisfactory passing of performance verification tests performed by srs labs, inc., or valence technology ltd. e-mail requests for performance spec ifications and testing rate schedule may be made to cslicense@srslabs.com. srs labs, inc. and vale nce technology, ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. all equipment manufactured using any cirrus logic chip containing enabled circle surrou nd? technology must carry the circle sur round? logo on the front panel in a manner approved in writing by srs labs, inc., or vale nce technology ltd. if the circle surround? logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by srs labs, inc., or valence technology, ltd. the rear panel of circle surround? products, users manuals, service manuals, and all advertising must all carry the legends as described in licensor's most current version of the circle surround trademark usage manual. spi is a trademark of motorola, inc. i 2 c is a registered trademark of philips semiconductor. ipod is a registered trademark of apple computer, inc.
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 3 confidential confidenti al draft delp h i table of contents 1. documentation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. code overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. hardware functional desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 dsp core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.1 dsp memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.2 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 on-chip dsp peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.1 digital audio input port (dai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.2 digital audio output port (dao) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.3 serial control port (i2c ? or spi?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.4 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.5 pll-based clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.6 hardware watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 dsp i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 termination requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.3 pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 application code security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. characteristics and spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 digital dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 thermal data (48 lqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 switching characteristics? reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 switching characteristics ? xti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.8 switching characteristics ? internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.9 switching characteristics ? serial control port - spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.10 switching characteristics ? serial control port - spi master mode . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.11 switching characteristics ? serial control port - i 2 c slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.12 switching characteristics ? serial control port - i 2 c master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.13 switching characteristics ? digital audio slave input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.14 switching characteristics ? dsd slave input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.15 switching characteristics ? digital audio output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. environmental, manufactur ing, & handling information . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. device pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 cs48520, 48-pin lqfp pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 cs48540, 48-pin lqfp pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3 cs48560,48-pin lqfp pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. package mechanical draw ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 48-pin lqfp package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
cs48500 data sheet 32-bit audio decoder dsp family 4 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi list of figures figure 1. reset timing ........ ................. ................ ................ ................ ................ ................ ................14 figure 2. xti timing........................................................................................................... .....................15 figure 3. serial control port - spi slave mode timing.......................................................................... .16 figure 4. serial control port - spi master mode timing......................................................................... 17 figure 5. serial control port - i 2 c slave mode timing ...........................................................................18 figure 6. serial control port - i 2 c master mode timing .........................................................................19 figure 7. digital audio input (dai) port timing diagram ........................................................................ 20 figure 8. direct stream digital - serial audio input timing.................................................................... .21 figure 9. direct stream digital - serial audio input timing for phase modulation mode........................21 figure 10. digital audio output data, input and output clock timing....................................................22 figure 11. digital audio port timing, mclk master mode .....................................................................22 figure 12. cs48520, 48-pin lqfp pinout ......................................................................................... .....24 figure 13. cs48540, 48-pin lqfp pinout ......................................................................................... .....25 figure 14. cs48560, 48-pin lqfp pinout ......................................................................................... .....26 figure 15. 48-pin lqfp package drawing ......................................................................................... ....27 list of tables table 1. cs48500 related documentation......................................................................................... ......5 table 2. device and firmware selection guide................................................................................... .....8 table 3. ordering information .................................................................................................. ...............23 table 4. environmental, manufacturing, & handling information............................................................23
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 5 confidential confidenti al draft delp h i 1. documentation strategy the cs48500 data sheet describes the cs48500 family of multichannel audio processors. this document should be used in conjunction with the following documents when evaluating or designing a system around the cs48500 family of processors. the scope of the cs48500 data sheet is primarily the hardware specif ications of the cs48500 family of devices. this includes hardware functionality, characteristic data, pinout, and packaging information. the intended audience for the cs48500 data sheet is the system pcb designer, mcu programmer, and the quality control engineer. document name description cs48500 data sheet this document cs48500 hardware user?s manual includes detailed system design information including typical connection diagrams, boot- procedures, pin descriptions, etc. an298 - cs48500 firmware user?s manual includes detailed firmware design information including signal processing flow diagrams and control api information dsp composer user?s manual includes detailed configuration and usage information for the gui development tool. table 1. cs48500 related documentation
cs48500 data sheet 32-bit audio decoder dsp family 6 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 2. overview the cs48500 dsp family is designed to provide high -performance post-processing and mixing of ditial audio. the dual clock domain provided on the pcm inputs allows for the mixing of audio streams with different sampling frequencies. the low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems. there are three devices comprising the cs48500 family. the cs48520, cs48540 and cs48560 are differentiated by the number of inputs and outputs av ailable. all dsps support dual input clock domains and dual audio processing paths. all dsps are avai lable in a 48-pin qfp package. please refer to ta bl e 2 on page 8 for the input, output, firmware features of each device. 2.1 licensing licenses are required for all of the 3 rd party audio processing algorithms listed in section 3. please contact your local cirrus logic sales representative for more information.
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 7 confidential confidenti al draft delp h i 3. code overlays the suite of software available for the cs48500 family c onsists of an operating system (os) and a library of overlays. the overlays have been divided into three main groups called matrix-processors, virtualizer- processors, and post-processors. all software components are defined below: 1. os/kernel - encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audi o-processing subroutines, error concealment, etc. 2. matrix-processor - any module that performs a matrix decode on pcm data to produce more output channels than input channels (2 ? n channels). examples are dolb y prologic iix and dts neo:6. generally speaking, these modules increase the number of valid channels in the audio i/o buffer. 3. virtualizer-processor - any module that encodes pcm data into fewer output channels than input channels (n ? 2 channels) with the effect of providing ?ph antom? speakers to represent the physical audio channels that were eliminated. examples are dolby headphone ? and dolby virtual speaker ? . generally speaking, these modules reduce the number of valid channels in the audio i/o buffer. 4. post-processors - any module that processes audio i/o buffer pcm data in-place after the matrix- or virtualizer-processors. examples are bass managem ent, audio manager, tone control, eq, delay, customer-specific effects, etc. the bulk of each overlay is stored in rom within the cs48500, but a small image is required to configure the overlays and boot the dsp. this small im age can either be stored in an external serial flash/eeprom, or downloaded via a host controller through the spi ? /i 2 c ? serial port. the overlay structure reduces the time required to reconfigure the dsp when a processing change is requested. each overlay can be reloaded independently without disturbing the other overlays. for example , when a new matrix-processor is selected, t he os, virtualizer-, and post-processors do not need to be reloaded ? only the new matrix-processor (the same is true for the other overlays). ta bl e 2 below lists the firmware available based on device selection. please refer an298, cs48500 firmware user?s manual for the latest listing of application codes and cirrus framework ? modules available.
cs48500 data sheet 32-bit audio decoder dsp family 8 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi note: refer to an298 for more information on software features device suggested application chanenel count input/output package cs4 8 520-cqz digital tv portable audio docking station portable dvd dvd mini / receiver multimedia pc speakers up to 4 channel in / 4 channel out 48-pin qfp cs4 8 540-cqz cs4 8 540-dqz cs48520 features plus 8 channel car audio dvd receiver up to 8 channel in / 8 channel out 48-pin qfp cs4 8 560-cqz cs4 8 560-dqz cs48540 features plus 12 channel car audio high-end digital tv dual source/dual zone sacd up to 12 channel in /12 channel out 48-pin qfp table 2. device and firmware selection guide
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 9 confidential confidenti al draft delp h i 4. hardware functional description 4.1 dsp core the cs48500 is a single-core dsp with separate x and y data and p code memory spaces. the dsp core is a high-performance, 32-bit, user-programmabl e, fixed-point dsp that is capable of performing two multiply-and-accumulate (mac) operations pe r clock cycle. the dsp core has eight 72-bit accumulators, four x- and four y-data registers, and 12 index registers. the dsp core is coupled to a flexible dma engine. the dma engine can move data between peripherals such as the serial control port (scp), digital audio input (dai) and digital audio output (dao), or any dsp core memory, all without the intervention of the dsp. the dma engine off loads data move instructions from the dsp core, leaving more mips available for signal processing instructions. cs48500 functionality is controlled by application codes that are stored in on-board rom or downloaded to the cs48500 from a hos t controller or external serial flash/eeprom. users can develop their applications using dsp co mposer to create the processing chain and then compile the image into a series of commands that are sent to the cs48500 through the scp. the processing application can either load modules (m atrix-processors, virtualizers, post-processors) from the dsps on-board rom, or custom firmware can be downloaded through the scp. the cs48500 is suitable for a variety of audio post -processing applications such as automotive head- ends, automotive amplifiers, and boom boxes. 4.1.1 dsp memory the dsp core has its own on-chip data and program ram and rom and does not require external memory for post-processing applications. the y-ram and p-ram share a single block of memory that can be configured to make y and p equal in size, or more memory can be allocated for y-ram in 2kword blocks. 4.1.2 dma controller the powerful 8-channel dma controller can move data between 8 on-chip resources. each resource has its own arbiter: x, y, and p rams/roms and the peripheral bus. modulo and linear addressing modes are supported, with flexible start address and increment controls. the service intervals for each dma channel, as well as up to 6 interrupt events, are programmable.
cs48500 data sheet 32-bit audio decoder dsp family 10 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 4.2 on-chip dsp peripherals 4.2.1 digital audio input port (dai) each version of the cs48500 support a differ ent number of input channels. refer to table 2 on page 8 for more details. the dai port supports a wide variety of data input formats at sample rates (fs) as high as 192 khz. the port is capable of accepting pcm or dsd formats. up to 32-bit word lengths are supported. dsd is supported and internally converted to pcm before pr ocessing. the dai also supports a time division multiplexed (tdm) one-line data mode, that packs pcm audio on a single data line (the total number possible depends on the ratio of sclk to lrclk and the version of chip. for example on the cs48520 only 4 ch of pcm are supported in one line mode and on the cs48560 up to 8 channels are supported.). the port has two independent slave-only clock domains. each data input can be independently assigned to a clock domain. the sample rate of the input clock domains can be determined automatically by the dsp, off-loading the task of monitoring the spdif re ceiver from the host. a time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 digital audio output port (dao) each version of the cs48500 support a different number of output channels. refer to table 2 on page 8 for more details. dao port supports pcm resolutions of up to 32-bits. the port supports sample rates (fs) as high as 192 khz. the port can be configured as an independent clock domain mastered by the dsp, or as a clock slave if an external mclk or sclk/lrclk source is available. one of the serial audio pins can be re- configured as a spdif transmitter that drives a bi-phase encoded s/pdif signal (data with embedded clock on a single line). 4.2.3 serial control port (i 2 c ? or spi ? ) the on-chip serial control port is capable of operating as master or slave in either spi ? or i 2 c ? modes. master/slave operation is chosen by mode select pins when the cs48500 comes out of reset. the serial clock pin can support frequencies as high as 25 mh z in spi mode (spi clock speed must always be (f dclk /2)). the cs48500 serial control port also includes a pin for flow control of the communications interface (#scp_bsy) and a pin to indicate when the dsp has a message for the host (#scp_irq). 4.2.4 gpio many of the cs48500 peripheral pins are multiplex ed with gpio. each gpio can be configured as an output, an input, or an input with interrupt. each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.2.5 pll-based clock generator the low-jitter pll generates integer or fractional multiples of a reference frequency which are used to clock the dsp core and peripherals. through a second pll divider chain, a dependent clock domain can be output on the dao port for driving audio converters. the cs48500 defaults to running from the external reference frequency and is switched to use the pll output after overlays have been loaded and configured, either through master boot from an exter nal flash or through host control. a built-in crystal oscillator circuit with a buffered output is provi ded. the buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 11 confidential confidenti al draft delp h i 4.2.6 hardware watchdog timer the cs48500 has an integrated watchdog timer that acts as a ?health? monitor for the dsp. the watchdog timer must be reset by the dsp before the counter expires, or the entire chip is reset. this peripheral ensures that the cs48500 will reset itself in the event of a temporary system failure. in stand- alone mode (i.e. no host mcu), the dsp will reboot fr om external flash. in slave mode (i.e. host mcu present) a gpio will be used to signal the host that the watchdog has expired and the dsp should be rebooted and re-configured. 4.3 dsp i/o description 4.3.1 multiplexed pins many of the cs48500 pins are multi-functional. fo r details on pin functionality please refer to the cs48500 hardware user?s manual . 4.3.2 termination requirements open-drain pins on the cs48500 must be pulled high for proper operation. please refer to the cs48500 hardware user?s manual to identify which pins are open-drai n and what value of pull-up resistor is required for proper operation. mode select pins on the cs48500 are used to select the boot mode upon the rising edge from reset. a detailed explanation of termination requirements for each communication mode select pin can be found in the cs48500 hardware user?s manual . 4.3.3 pads the cs48500 i/os operate from the 3.3 v supply and are 5 v tolerant. 4.4 applicati on code security the external program code may be encrypted by the programmer to protect any intellectual property it may contain. a secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. please contact yo ur local cirrus representative for details.
cs48500 data sheet 32-bit audio decoder dsp family 12 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5. characteristics and specifications note: all data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. all data sheet typical parameters are measured under the following conditions: t = 25 c, c l = 20 pf, vdd = vdda = 1.8 v, vddio = 3.3 v, gndd = gndio = gnda = 0 v. 5.1 absolute maximum ratings (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) caution: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 5.2 recommended o perating conditions (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) note: it is recommended that the 3.3 v io supply come up ahead of or simultaneously with the 1.8 v core supply. 5.3 digital dc characteristics (measurements performed under static conditions.) parameter symbol min max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio ?0.3 ?0.3 ?0.3 - 2.0 3.6 3.6 0.3 v v v v input pin current, any pin except supplies i in -+/- 10ma input voltage on pll_ref_res v filt -0.3 3.6 v input voltage on i/o pins v inio -0.3 5.0 v storage temperature t stg ?65 150 c parameter symbol min typ max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio 1.71 3.13 3.13 1.8 3.3 3.3 0 1.89 3.46 3.46 v v v v ambient operating temperature - cqz - dqz t a 0 - 40 - + 70 + 85 c parameter symbol min typ max unit high-level input voltage v ih 2.0 - - v low-level input voltage, except xti v il --0.8v low-level input voltage, xti v ilxti --0.6v input hysteresis v hys 0.4 v high-level output voltage (i o = -2ma), except xti v oh vddio * 0.9 - - v low-level output voltage (i o = 2ma), except xti v ol --vddio * 0.1v input leakage current (all digital pins with internal pull-up resistors disabled) i in --5 a input leakage current (all digital pins with internal pull-up resistors enabled, and xti) i in-pu --56 a
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 13 confidential confidenti al draft delp h i 5.4 power supply characteristics (measurements performed under operating conditions) 5.5 thermal data (48 lqfp) notes: 1. two-layer board is specified as a 76 mm x 11 4 mm, 1.6 mm thick fr-4 material with 1-oz. copper covering 20 % of the top & bottom layers. 2. four-layer board is specified as a 76 mm x 114 mm, 1.6 mm thick fr-4 material with 1-oz. copper covering 20 % of the top & bottom layers and 0.5-oz . copper covering 90 % of the internal power plane & ground plane layers. 3. to calculate the die temperat ure for a given power dissipation j = ambient temperature + [ (power dissipation in watts) * ja ] 4. to calculate the case temperature for a given power dissipation c = j - [ (power dissipation in watts) * jt ] parameter min typ max unit operational power supply current: vdd: core and i/o operating 1 vdda : p ll operating vddio: with most ports operating total operational power dissipation: standby power supply current: vdd: core and i/o not clocked vdda: pll halted vddio: all connected i/o pins 3-stated by other ics in system total standby power dissipation: 1.dependent on application firmware and dsp clock speed. - - - - - - - 203 8 27 469 100 1 15 350 - - - - - - - ma ma ma mw a a a w parameter symbol min typ max unit thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 ja - - 63.5 54 - - c / watt thermal resistance (junction to top of package) two-layer board 1 four-layer board 2 jt - - 0.70 0.64 - - c / watt
cs48500 data sheet 32-bit audio decoder dsp family 14 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5.6 switching char acteristics? reset parameter symbol min max unit reset# minimum pulse width low t rstl 1- s all bidirectional pins high-z after reset# low t rst2z -100ns configuration pins set up before reset# high t rstsu 50 - ns configuration pins hold after reset# high t rsthld 20 - ns figure 1. reset timing reset# t rst2z t rstl t rstsu t rsthld hs[3:0] all bidirectional pins
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 15 confidential confidenti al draft delp h i 5.7 switching char acteristics ? xti 5.8 switching characteris tics ? internal clock parameter symbol min max unit external crystal operating frequency f xtal 10 30 mhz xti period t clki 33.3 100 ns xti high time t clkih 13.3 - ns xti low time t clkil 13.3 - ns external crystal load capacitance (parallel resonant) 1 1.c l refers to the total load capacitance as specified by the crystal manufacturer. crystals which require a c l outside this range should be avoide d. the crystal oscillator circuit de sign should follo w the crystal man- ufacturer?s recommendation for load capacitor selection. c l 10 18 pf external crystal equivale nt series resistance esr 50 ? figure 2. xti timing parameter symbol min max unit internal dclk frequency 1 cs4852x-cqz cs4854x-cqz cs4856x-cqz cs4852x-dqz cs4854x-dqz cs4856x-dqz 1. after initial power-on reset, f dclk = f xtal . after initial kickstart commands, the pll is locked to max f dclk and remains locked until the next power-on reset. f dclk - f xtal f xtal f xtal f xtal f xtal 150 150 150 150 150 mhz internal dclk period 1 cs4852x-cqz cs4854x-cqz cs4856x-cqz cs4852x-dqz cs4854x-dqz cs4856x-dqz dclkp - 6.7 6.7 6.7 6.7 6.7 6.7 1/f xtal 1/f xtal 1/f xtal 1/f xtal 1/f xtal 1/f xtal ns t clkih t clkil t clki xti
cs48500 data sheet 32-bit audio decoder dsp family 16 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5.9 switching character istics ? serial contro l port - spi slave mode . parameter symbol min typical max units scp_clk frequency 1 1.the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware applica- tion. flow control using the scp_bsy# pin should be implemented to pr event overflow of the input data buffer. f spisck -25mhz scp_cs# falling to scp_clk rising t spicss 24 - ns scp_clk low time t spickl 20 - ns scp_clk high time t spickh 20 - ns setup time scp_mosi input t spidsu 5-ns hold time scp_mosi input t spidh 5-ns scp_clk low to scp_miso output valid t spidov -8ns scp_clk falling to scp_irq# rising t spiirqh -20ns scp_cs# rising to scp_irq# falling t spiirql 0ns scp_clk low to scp_cs# rising t spicsh 24 - ns scp_cs# rising to scp_miso output high-z t spicsdz -20 ns scp_clk rising to scp_bsy# falling t spicbsyl -3 * dclkp+20 ns figure 3. serial control po rt - spi slave mode timing scp_bsy# scp_cs# scp_clk scp_mosi scp_miso scp_irq# 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spibsyl t spiirql t spiirqh f spisck t spicsdz
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 17 confidential confidenti al draft delp h i 5.10 switching character istics ? serial control port - spi master mode . parameter symbol min typical max units scp_clk frequency 1 1.the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware applica- tion. f spisck -25mhz scp_cs# falling to scp_clk rising 2 2.scp_clk period refers to the perio d of scp_clk as being used in a given application. it does not refer to a tested parameter t spicss - 11*dclkp + (scp_clk period)/2 -ns scp_clk low time t spickl 20 - ns scp_clk high time t spickh 20 - ns setup time scp_miso input t spidsu 9-ns hold time scp_miso input t spidh 5-ns scp_clk low to scp_mosi output valid t spidov -8ns scp_clk low to scp_cs# falling t spicsl 7-ns scp_clk low to scp_cs# rising t spicsh - 11*dclkp + (scp_clk period)/2 -ns bus free time between active scp_cs# t spicsx 3*dclkp - ns scp_clk falling to sc p_mosi output high-z t spidz -20ns figure 4. serial control port - spi master mode timing ee_cs# scp_clk scp_miso scp_mosi 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spicsx f spisck t spidz t spicsl
cs48500 data sheet 32-bit audio decoder dsp family 18 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5.11 switching characteristics ? serial control port - i 2 c slave mode parameter symbol min typical max units scp_clk frequency 1 1.the specification f iicck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware applica- tion. flow control using the scp_bsy# pin should be implemented to pr event overflow of the input data buffer. f iicck - 400 khz scp_clk low time t iicckl 1.25 - s scp_clk high time t iicckh 1.25 - s scp_sck rising to scp_sda rising or falling for start or stop condition t iicckcmd 1.25 s start condition to scp_clk falling t iicstscl 1.25 - s scp_clk falling to stop condition t iicstp 2.5 - s bus free time between stop and start conditions t iicbft 3-s setup time scp_sda input valid to scp_clk rising t iicsu 100 ns hold time scp_sda inpu t after scp_clk falling t iich 20 - ns scp_clk low to scp_sda out valid t iicdov -18ns scp_clk falling to scp_irq# rising t iicirqh -3 * dclkp + 40 ns nak condition to scp_irq# low t iicirql 3 * dclkp + 20 ns scp_clk rising to scb_bsy# low t iicbsyl -3 * dclkp + 20 ns figure 5. serial control port - i 2 c slave mode timing scp_bsy# scp_clk scp_sda scp_irq# 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb t iicirqh t iicirql 8 ack msb t iicstp 6 t iiccbsyl t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 19 confidential confidenti al draft delp h i 5.12 switching characteristics ? serial control port - i 2 c master mode parameter symbol min max units scp_clk frequency 1 1.the specification f iicck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware applica- tion. f iicck - 400 khz scp_clk low time t iicckl 1.25 - s scp_clk high time t iicckh 1.25 - s scp_sck rising to scp_sda rising or falling for start or stop condition t iicckcmd 1.25 s start condition to scp_clk falling t iicstscl 1.25 - s scp_clk falling to stop condition t iicstp 2.5 - s bus free time between stop and start conditions t iicbft 3-s setup time scp_sda input valid to scp_clk rising t iicsu 100 ns hold time scp_sda inpu t after scp_clk falling t iich 20 - ns scp_clk low to scp_sda out valid t iicdov -18ns figure 6. serial control port - i 2 c master mode timing scp_clk scp_sda 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb 8 ack msb t iicstp 6 t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs48500 data sheet 32-bit audio decoder dsp family 20 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5.13 switching charact eristics ? digital audio slave input port parameter symbol min max unit dai_sclk period t daiclkp 40 - ns dai_sclk duty cycle - 45 55 % setup time dai_datan t daidsu 10 - ns hold time dai_datan t daidh 5-ns figure 7. digital a udio input (dai) port timing diagram dai_sclk dai_datan t daidh t daidsu
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 21 confidential confidenti al draft delp h i 5.14 switching characteris tics ? dsd slave input port parameter symbol min typ max unit mclk duty cycle - 40 - 60 % dsd_sclk pulse width low t sclkl 78 - - ns dsd_sclk pulse width high t sclkh 78 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) - - 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns dsd clock to data transition (phase modulation mode) t dpm -20 - 20 ns figure 8. direct stream digita l - serial audio input timing dpm t dsd_a, dsd_b dsd_sclk (64fs) dsd_sclk (128fs) dpm t figure 9. direct stream digital - serial audio input timing for phase modulation mode
cs48500 data sheet 32-bit audio decoder dsp family 22 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 5.15 switching characteristics ? digital audio output port parameter symbol min max unit dao_mclk period t daomclk 40 - ns dao_mclk duty cycle - 40 60 % dao_sclk period for master or slave mode 1 1.master mode timing specifications are characterized, not production tested. t daosclk 40 - ns dao_sclk duty cycle for master or slave mode 1 -4060% master mode (output a1 mode) 1,2 2.master mode is defined as the cs48500 driving bo th dao_sclk, dao_lrclk. when mclk is an input, it is divided to produce dao_sclk, dao_lrclk. dao_sclk delay from dao_mclk rising edge, dao_mclk as an input t daomsck -19ns dao_lrclk delay from dao_sclk transition, respectively 3 3.this timing parameter is defined from the non-ac tive edge of dao_sclk. the active edge of dao_sclk is the point at which the data is valid. t daomstlr -8ns dao1_data[3..0], dao2_data[1..0] delay from dao_sclk transition 3 t daomdv -10ns slave mode (output a0 mode) 4 4.slave mode is defined as dao_sclk, dao_lrclk driven by an external source. dao1_data[3..0], dao2_data[1..0] delay from dao_sclk transition 3 t daosdv 15 ns figure 11. digital audio port timing, mclk master mode dao_mclk dao_sclk dao_lrclk daon_datan t daomclk t daomsck t daomdv , t daosdv t daomstlr t daomstlr
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 23 confidential confidenti al draft delp h i 6. ordering information the cs48500 family part number is described as follows: cs485ni-xyz where n - product number variant i - rom id number x - product grade y - package type z - lead (pb) free note: please contact the factory for availab ility of the -d (autom otive grade) package. 7. environmental, manufactur ing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. table 3. ordering information part no. grade temp. range package cs48520-cqz commercial 0 to +70 c 48-pin lqfp cs48540-cqz commercial 0 to +70 c cs48540-dqz automotive -40 to +85 c cs48560-cqz commercial 0 to +70 c cs48560-dqz automotive -40 to +85 c table 4. environmental, manufacturing, & handling information model number peak reflow temp msl rating* max floor life cs48520-cqz 260 c 3 7 days cs48540-cqz cs48540-dqz cs48560-cqz cs48560-dqz
cs48500 data sheet 32-bit audio decoder dsp family 24 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 8. device pinout diagrams 8.1 cs48520, 48-pin lqfp pinout diagram xto xti gnda pll_ref_res vdda (3.3v) gpio1 gpio2 gpio16, dai1_data0 gpio0 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, xmta gpio3, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk gpio18, dao_mclk dai1_sclk vdd1 gnd1 dao_sclk gpio4, hs2 reset# vddio1 gndio1 gpio6, dao2 _data0, hs3 gpio7, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, dai2_data0 cs48520 48 lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48 figure 12. cs48520, 48-pin lqfp pinout
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 25 confidential confidenti al draft delp h i 8.2 cs48540, 48-pin lqfp pinout diagram xto xti gnda pll_ref_res vdda (3.3v) gpio1, dai1_data2 gpio2 gpio16, dai1_data0 gpio0, dai1_data1 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, xmta gpio3, dao1_ data1, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk gpio18, dao_mclk dai1_sclk vdd1 gnd1 dao_sclk gpio4, dao1_ data2, hs2 reset# vddio1 gndio1 gpio6, dao2_data0, hs3 gpio7, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, d ai2 _d a t a 0 cs48540 48 lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48 figure 13. cs48540, 48-pin lqfp pinout
cs48500 data sheet 32-bit audio decoder dsp family 26 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 8.3 cs48560,48-pin lq fp pinout diagram xto xti gnda pll_ref_res vdda (3.3v) gpio1, dai1_data2, tm2, dsd2 gpio2, dai1_data3, tm3, dsd3 gpio16, dai1_data0, tm0, dsd0 gpio0, dai1_data1, tm1, dsd1 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, dao1_data3, x mta gpio3, dao1_ data1, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk, dai1_data4, dsd5 gpio18, dao_mclk dai1_sclk, dsd-clk vdd1 gnd1 dao_sclk gpio4, dao1_ data2, hs2 reset# vddio1 gndio1 gpio6, dao2 _data0, hs3 gpio7, dao2_d ata1, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, dai2_data0, dsd4 cs48560 48 lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48 figure 14. cs48560, 48-pin lqfp pinout
cs48500 data sheet 32-bit audio decoder dsp family ds734a3 ? copyright 2006 cirrus logic, inc. 27 confidential confidenti al draft delp h i 9. package mechanical drawings 9.1 48-pin lqfp package drawing 48 ld lqfp (7 x 7 x 1.4 mm body) number of leads 48 min nom max a1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 d 9.00 bsc d1 7.00 bsc e 0.50 bsc e 9.00 bsc e1 7.00 bsc theta 0 7 l 0.45 0.60 0.75 l1 1.00 ref notes: 1) reference document: jedec ms-026 2) all dimensions are in millimeters and controlling dimension is in millimeters. 3) d1 and e1 do not include mold flash which is 0.25 mm max. per side.a1 4) dimension b does not include a total allowable dambar protrusion of 0.08 mm max. figure 15. 48-pin lqfp package drawing
cs48500 data sheet 32-bit audio decoder dsp family 28 ? copyright 2006 cirrus logic, inc. ds734a3 confidential confidenti al draft d elphi 10. revision history revision date changes a1 jul 2006 advance release. a2 jul 2006 updated pinout definition for pins 26 and 27. updated typical power numbers. a3 dec 5 2006 updated sections 2.0, 4.2.1, 5.8, table 3, table 4, to show new device number- ing scheme. updated sections 8.1, 8.2, 8.3.

▲Up To Search▲

Price & Availability of CS48520-CQZR

	To Download CS48520-CQZR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .